Arquiteturas de hardware de baixa potência para codificação de vídeo usando operadores aritméticos de codificação híbrida

Abstract

Video coding is one of the rapidly expanding areas. More and more companies are investing in this area. The transmission and storage of videos in raw form is costly and often impractical, as in the case of ultra high definition videos (UHD). With this goal the video encoders and video coding standards arise, such as the HEVC, focus of this work. With the HEVC it is possible to compress a video with approximately half the number of bits that its predecessor, the H.264/AVC, maintaining practically the same quality characteristics of the original video. In this way, the development of specific integrated circuits for video processing is an important activity in the area of digital systems research, since software solutions generally do not achieve the performance and energy efficiency necessary for several applications, especially for mobile devices. Motivated by the need for low power consumption, this work applies the Hybrid coding concept, whose purpose is to divide the operands into groups of m bits, coding each group using the Gray code, and using the behavior of the binary code to propagate the carry between the groups. Thus, the number of transitions in each group can be reduced and a regular structure can be obtained, where the least significant groups of the result depend only on the least significant groups of operators, thus reducing the number of transitions between bits. The goal of this work is the implementation of hardware architectures for modules of the HEVC video coding standard using arithmetic operators of hybrid coding, aiming the low energy consumption. The study explores the feasibility of using hybrid coding in video coding, and quantifying the gain in power and energy of such operators. The work seeks to identify which HEVC modules are most suitable for the employment of such operators, aiming for greater reductions in energy consumption. Hardware architectures for the Interpolation (for fractional motion estimation), the calculation of SAD - Sum of Absolute Differences, and for Quantization, were developed. In addition, the work proposes two new hybrid adders, and their use in video coding module architectures. Results show a power reduction of the architectures using hybrid encoding arithmetic operators, when compared to the same architecture using conventional arithmetic operators, with binary coding.