Otimização de estruturas de borboletas para arquitetura de transformada rápida de Fourier de baixa dissipação de potência

Abstract

In the FFT computation, the butterflies play a central role, since they allow calculation of complex terms. In this calculation, involving multiplications of input data with appropriate coefficients, the optimization of the butterfly can contribute for the reduction of power consumption of FFT architectures. In this work, different and dedicated structures for the 16 bit-width radix- 2, radix-4 and split-radix DIT butterflies are implemented, where the main goal is to minimize the number of arithmetic operators in order to produce power-efficient structures. Firstly, we improve a radix-2 butterfly previously presented in literature, reducing one adder and one subtractor in the structure. After, part of this optimized radix-2 butterfly is used to reduce the number of real multipliers in both radix-4 and split-radix butterflies. In this work, multi-operands addition schemes were exploited in order to improve the efficiency of the FFT butterflies. Combinations of simultaneous addition of 3, 5 and 7 operands are inserted in the structures of the butterflies in order to produce power-efficient structures. For the multi-operand additions, Carry Save Adder (CSA), and adder compressors are used. The main results show that the use of part of the optimized radix-2 into the radix-4 and split-radix leads to the reduction of power consumption for these structures. Moreover, the use of Carry Save Adder reduces still more the power dissipation of the optimized butterflies structures