Exploração arquitetural nas métricas de similaridade para codificadores de vídeo do padrão HEVC

Abstract

The HEVC video compression standard is one of the newest standards. It achieves higher compression ratio compared to existing standards and doubles the compression ratio of the previous standard, the H.264/AVC (Advanced Video Coding). In video encoder, the Motion Estimation and Intra Prediction modules are present and uses intensively the follow similarity metrics for mode decision: the Sum of Absolute Differences and the Sum of Absolute Transformed Differences. The intense use of these metrics represents the major part of the computational complexity of the HEVC video encoder. The aim of this work is to explore hardware architectures for SAD and SATD similarity metrics using power consumption reduction techniques. For the SATD metric two studies were performed: the first study focuses on the architectural exploration at different levels of parallelism of the 8x8 Hadamard Transform; the second study aims at the implementation of architectures based on multiple sizes of the Hadamard Transform. As power reduction techniques, adders compressor were used in the SATD architectures. Adders compressor were also used in different recombinations of SAD metric. All architectures presented in this work were implemented in hardware description language VHDL and synthesized for ASIC in Nangate’s 45nm technology using the Cadence RTL Compiler tool. The power estimation of the architectures was obtained using real inputs extracted from the reference software of the HEVC standard. Comparative analyzes were performed between these architectures, as well as comparisons with architectures state-of-the-art. The architectures using adders/subtractors compressors compared to architectures using adder from the synthesis tool have a power reduction of 16.3 % for the sequential, 21.1 % for the semi-parallel and 26.6 % for the parallel for the SATD based on HT 8x8 and 10.07 % for SATD based on multiple sizes of HT. For the SAD architecture using 8: 2 compressor adders the power reduction was 61.8 %.