Circuitos Multiplicadores Array de Baixo Consumo de Potência Aplicados a Filtros Adaptativos

Abstract

The main goal of this work is the implementation and analyzes of new array multiplier architectures. These new architectures were recently presented in the scientific community by including different power reduction techniques, such as the use of efficient adder circuits and the optimization of the dedicated multiplication structures that allow the multiplication operation in the radix 2m. The new multipliers operate in 2´s complement and keep the same regularity presented by a conventional array multiplier. The architectures operate in the radix 2m, where m represents the group of bits multiplied at a time. In a conventional array multiplier, where the multiplication is performed bit by bit, m assumes value equal 1 (radix 2 operation). In this work, the new multiplier architectures operate in different radices, leading to a reduction in the number of partial product lines, enabling higher performance and power reduction in the multipliers. The 16, 32 and 64 bit width multipliers were described in textual language (gate level), and the comparisons between the multipliers are preformed in terms of area, delay and power consumption by using SIS environment (for area and delay results) and SLS tool (for power consumption estimation). In this work we have applied the proposed optimized multipliers in digital filtering algorithms such as finite impulse response (FIR) and dedicated architecture for the LMS (Least Mean Square) adaptive filtering